Configurable logic circuits such as field programmable gate arrays (“FPGAs”) historically may take a considerable time period to load one or more configurations, typically referred to as configuration bit images (or bit images), which are typically stored in adjacent FLASH memory (as a type of nonvolatile memory). This problem is magnified when many FPGAs require configuration, such as upon system power up or when another, different application is to be performed by the FPGAs, especially for supercomputing applications.
Storing a bit image in a nonvolatile memory (such a FLASH memory) local to a given FPGA also may be comparatively slow for configuring an FPGA, and in addition, such local storage does not help when a bit image for an application is modified or updated, or when another new or different application is to be performed on the FPGA. For such systems, the FLASH memory must be updated, which also may take a considerable period of time, i.e., minutes rather than seconds, and the updated bit image must be reloaded into the FPGA, and both of which again are compounded when multiple FPGAs with local nonvolatile memory are to be configured, such as 50-1000 FPGAs, for example and without limitation.
Accordingly, a need remains for a system having both hardware and software co-design to provide for rapid loading and updating of FPGA configurations or configuration bit images. Such a system should further provide for minimal host involvement, and for significantly parallel and rapid configuration.